mad-dev July 2004

mad-dev@lists.mars.org

9 participants
15 discussions

Qns abt MAD Library support for ARM environment
by balaji shanmugam 20 Jul '04

20 Jul '04

Hi I have recently started using the MAD decoder. My requirement is to use the MP3 library for the ARM 32 bit processor environement. I have compiled the library with the option FPM_ARM selected (I have modified the MACRO functions for my compiler support keeping the assembly instructions the same). But the audio output was not clear at all. Then I had selected FPM_DEFAULT. With that I am able to hear a feeble (but with noise) audio. /**** mad_f_mul ****/ #define FPM_ARM # define SIZEOF_INT 4 # define SIZEOF_LONG 4 # define SIZEOF_LONG_LONG 8 # define MAD_F_FRACBITS 28 #define MAD_F_SCALEBITS MAD_F_FRACBITS static mad_fixed_t mad_f_mul(mad_fixed_t x,mad_fixed_t y) { mad_fixed_t result; mad_fixed64hi_t hi; mad_fixed64lo_t lo; _asm(-1000," smull %0,%1,%3,%4 movs %0,lsr(%0,%5) adc %2,%0,lsl(%1,%6) ", __reg_gen(__obj_modify(lo)), __reg_gen(__obj_modify(hi)), __reg_gen(__obj_assign(result)), __reg_gen(x), __reg_gen(y), MAD_F_SCALEBITS, (32 - MAD_F_SCALEBITS) ); return result; } /****Ends****/ I like to know if I am missing something? Thanks Balaji Shanmugam _________________________________________________________________ Reach out to millions of buyers. http://go.msnserver.com/IN/52047.asp With zero investment.

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determining the first scale factor band with short windows
by Rafael Ávila de Espíndola 13 Jul '04

13 Jul '04

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Rob, I noticed that libmad count up to 36 in III_reorder to determine the first scale factor band that should be reordered in a mixed block. The attached patch precomputes this. I don't expect it to improve performance in any measurable way but (IMHO) it makes the code a bit easier to read. Thanks for libmad, Rafael Ávila de Espíndola -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.4 (GNU/Linux) iD8DBQFA8zvTLlrfGJ8JUHwRAlmMAJwKzXgUoXPUM+U8u2l4cByyHPjRYgCfWuEZ Jw7Qs4lVqbC9wNHixrDaqFs= =Pu6p -----END PGP SIGNATURE-----

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16bit MAD
by Erik Gustavsson 02 Jul '04

02 Jul '04

Would it be possible to convert MAD into a (limited compliance) decoder using mostly 16bit fixed-point math? Specifically I'd like to port MAD to a ADI Blackfin DSP, which has 32bit registers and ALU but only 16x16 multipliers (with 40bit accumulators).

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RE: [mad-dev] A little help needed on code optimisation to deal with delay slots
by Joolz [RSD] 02 Jul '04

02 Jul '04

I would like to have a look please Gregory. I have already started the port // MLO( x, y); ld %r0, [x] ld %r1, [y] mul64 %r0, %r1 ld %r2, [%mhi] // MLA( x1, y1); ld %r0, [x1] ld %r1, [y1] mul64 %r0, %r1 add %r2, [%mhi] // MLA( x2, y2); ld %r0, [x2] ld %r1, [y2] mul64 %r0, %r1 add %r2, [%mhi] Into ld %r0, [x] ld %r1, [y] mul64 %r0, %r1 ld %r0, [x1] ld %r1, [y1] ld %r2, [%mhi] mul64 %r0, %r1 ld %r0, [x2] ld %r1, [y2] add %r2, [%mhi] mul64 %r0, %r1 Saves 2 cycles per multiply, only another 8 to go Best Regards Julian Gardner RSD Communications Ltd ============================ Please do not send me any html messages as these may be deleted at our mail server without notice to sender or recipient. Please ONLY send me file attachments with any messages with extensions .zip, .rar, or .pdf as any other file types may be deleted at our mail server without notice to sender or recipient. > -----Original Message----- > From: Grigory A. [mailto:Ryhor@tut.by] > Sent: Friday, July 02, 2004 2:34 AM > To: Joolz [RSD] > Cc: mad-dev(a)lists.mars.org > Subject: Re: [mad-dev] A little help needed on code > optimisation to deal with delay slots > > Hi Joolz! > > You have BIG problem :) 10 cycles stall every mul. > The most "multiplication consuming" functions are > - IMDCT - actually it isn't too much > - synthesis filter > > last one has a lot of multiplication > all other relatively free from mult operation. May be stereo > processing has a little. > > If you have short of calculation power I can recommend you to > do same as I did. I've separated calculation functions and > implement them on asm. > I can send the source code of of MAD with such improvements > that I used for > - tms320vc55xx and > - sp3R5 3DSP cores. > > > -- > Best regards, > Grigory mailto:Ryhor@tut.by > >

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A little help needed on code optimisation to deal with delay slots
by Joolz [RSD] 02 Jul '04

02 Jul '04

I have ported the library to our hardware platform ( a set-top box with ide interface and ARC8 processor) but I have found that we are running short of horsepower. The problem stems from the fact that when I use the multiplier it stalls the chip for 10cycles on every multiply mul64 %r0, %r1 lsl %r0, [%mhi], 4 --> Stalls until multiplier finishes I have started looking at reordering the code as I can use other instructions in these 10 cycles <from synth.c dct32:282> // t69 = t33 + t34; t89 = MUL(t33 - t34, costab4); mad_f_mul_j( t33 - t34, costab4); // We have 10 cycles to wait t69 = t33 + t34; // 2-3 t70 = t35 - t36; // 2-3 t89 = mad_f_mul_r(); // t70 = t35 + t36; t90 = MUL(t35 - t36, costab28); // t70 = t35 - t36; mad_f_mul_j( t70, costab28); // We have 10 cycles to wait t70 = t35 + t36; // 2-3 t113 = t69 + t70; // 2-3 t71 = t37 - t38; // 2-3 t90 = mad_f_mul_r(); This gives me savings of around 6 cycles per multiply, so we only lose 4 cycles. What I would like know is which routine/s should I convert first to save the maximum amount of time Joolz

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mad-dev July 2004