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682 discussions

TI 55X Implementation
by balaji shanmugam 29 Jul '04

29 Jul '04

Hi Could anyone send me across information about porting the MADLIB for 16 bit fixed point DSPs (either the 54x or 55x) Regards Balaji Shanmugam _________________________________________________________________ NRIs ! http://go.msnserver.com/IN/52616.asp FREE money transfers to India.

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Streaming rate matching
by Nigel Sinfield 28 Jul '04

28 Jul '04

Hi, I'm planning to use MAD in a streaming application. I have no control over the incoming data rate, although it is ostensibly CBR data with a fixed sample rate. Similarly, the processing rate of the decoded samples is controlled by the DAC. So inevitably sooner or later I'll get a buffer overflow or underflow. Any suggestions how best to handle this? I'm sure someone must have been here before and I don't want to reinvent wheels. Thanks. The contents of this email and any attachments are sent for the personal attention of the addressee(s) only and may be confidential. If you are not the intended addressee, any use, disclosure or copying of this email and any attachments is unauthorised - please notify the sender by return and delete the message. Any representations or commitments expressed in this email are subject to contract. ntl Group Limited

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Number format for sbsamples from IMDCT (Q4.28 to 16 bit PCM samples)
by balaji shanmugam 27 Jul '04

27 Jul '04

Hi Rob I am new in using the MAD Library and upon working with the code, I have got doubt in the Scaling (1st operand shifted right by 12 and 2nd operand shifted right by 16) being done during the mad_f_mul operation. I like to know about the sbsamples from the IMDCT routine. Is it in Q4.28 format. If so why we need to scale it down during SYNTHESIS Filter operation. I have read the comments in fixed.h telling that " * The scale factors are constant as this is not used with SSO. * * Pre-rounding is required to stay within the limits of compliance. " I like to know how this scaling has been taken care in the further calculations. Please find below my doubt. I have defined as FPM_DEFAULT and doesnt define OPT_SPEED.[OPT_SSO will be defined as FPM_DEFAULT is defined]. With that the mad_f_mul (A,B) is defined as [((A+(1L<<11))>>12) * ((B+(1L<<15))>>16)] This has been used during the synth_full operation. When the synth_full function calls the dct32() function, sbsamples<2><2><576> (in Q28.4 format) from IMDCT is passed on to the function where it will be multiplied with costab<1..31>. During this multiplication the mad_f_mul MACRO is used. After that the result from dct32 is stored as the filter output. While storing the filter output, the multiplied value is scaled down by a factor of 12. Then windowing[D array values being scaled down by 12] was applied over the filter ouput and the PCM output is stored with a scale down of 2. The operation of SSO is understandable but the intial scaling that happens with the mad_f_mul MACRO needs explanation. Thanks in advance Balaji Shanmugam _________________________________________________________________ News, views and events. Hot downloads n pictures. http://www.msn.co.in/Cinema/ Get it all at MSN Cinema!

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Re: [mad-dev] MAD library for TI-54X DSPs
by balaji shanmugam 21 Jul '04

21 Jul '04

Hi I too have started doing most of the stuffs in asm rather than going for C functions. The first thing that I am concentrating is the SYNTH function. Bt still since i am following the LONG calculation(Q28.4) instead of Q15.1, mine is still vulnerable for timing issues. It will be gr8 help if you could send me across your version (16 bit arithmetic and Q15.1 for 55X) of MAD decoder for my reference. Thanks in advance Balaji Shanmugam >From: "Grigory A." <Ryhor(a)tut.by> >Reply-To: "Grigory A." <Ryhor(a)tut.by> >To: "balaji shanmugam" <balajiami(a)hotmail.com> >CC: mad-dev(a)lists.mars.org >Subject: Re: [mad-dev] MAD library for TI-54X DSPs >Date: Wed, 21 Jul 2004 09:58:50 +0900 > >Hi Balaji! > >I have ported MAD to TI-55xx. I used Q1.15 format and 16 bits >arithmetics for all calculation. As result of this is: > >limited accuracy ISO/IEC 11172-3 audio decoder > >according to >http://www.underbit.com/resources/mpeg/audio/compliance/ > >Yes - synthesis step of decoding is most calculation intensive part. >I've used a little different method to port MAD to TI-55xx DSP - >instead of providing "arithmetics macro" for given platform I've >rewrite on DSP asm all calculation intensive functions (8 or 9 ?). So >I think this is a better way in case if someone need close to optimal >implementation for given hardware platform. Only you need to do is >to rewrite these asm functions for your platform. > >I can send you my implementation of decoder. And maybe it is better to put >it to >MAD site? Because I've sent it several times before to other people >and this question is arisen again and again :). In additional I have >same style implementation of MAD for sp3R5m DSP (www.3dsp.com) this >one is 32 DSP core and in this case "fully compliant" decoder is >obtained. > > > >Tuesday, July 20, 2004, 11:25:28 PM, you wrote: > >bs> Hi >bs> I am trying to port the MAD library for the TI-54X DSP and running into >bs> tight timing issues. When analysed, I found out that the 54X DSP takes >more >bs> instructions to perform LONG calculations at the SYNTHESIS FILTER Bank >stage >bs> as it is a 16 bit processor [but with a 40 bit accumulator]. As it is >bs> required to perform 72 times the DCT32 and the remaining MATRIX >calculations >bs> at the SYNTH stage, I like to optimize the synthesis filter bank. >bs> I am not sure about using the Q28.4 format being used by MAD. Is there >bs> anyway we can use the Q15.1 format for the calculations? >bs> I like to know is there any hints or clues for the LONG calculations >that I >bs> can make use of during my 54X porting phase. Also any thought about >using >bs> the NORM instruction to round the final samples to 16 bit will be >helpful. > >bs> Regards >bs> Balaji Shanmugam > >bs> _________________________________________________________________ >bs> Marriage? >bs> http://www.bharatmatrimony.com/cgi-bin/bmclicks1.cgi?74 Join >bs> BharatMatrimony.com for free. > > > >-- >Best regards, > Grigory mailto:Ryhor@tut.by > _________________________________________________________________ Get head-hunted by 10,000 recruiters. http://go.msnserver.com/IN/46246.asp Post your CV on naukri.com today.

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MAD library for TI-54X DSPs
by balaji shanmugam 21 Jul '04

21 Jul '04

Hi I am trying to port the MAD library for the TI-54X DSP and running into tight timing issues. When analysed, I found out that the 54X DSP takes more instructions to perform LONG calculations at the SYNTHESIS FILTER Bank stage as it is a 16 bit processor [but with a 40 bit accumulator]. As it is required to perform 72 times the DCT32 and the remaining MATRIX calculations at the SYNTH stage, I like to optimize the synthesis filter bank. I am not sure about using the Q28.4 format being used by MAD. Is there anyway we can use the Q15.1 format for the calculations? I like to know is there any hints or clues for the LONG calculations that I can make use of during my 54X porting phase. Also any thought about using the NORM instruction to round the final samples to 16 bit will be helpful. Regards Balaji Shanmugam _________________________________________________________________ Marriage? http://www.bharatmatrimony.com/cgi-bin/bmclicks1.cgi?74 Join BharatMatrimony.com for free.

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Qns abt MAD Library support for ARM environment
by balaji shanmugam 20 Jul '04

20 Jul '04

Hi I have recently started using the MAD decoder. My requirement is to use the MP3 library for the ARM 32 bit processor environement. I have compiled the library with the option FPM_ARM selected (I have modified the MACRO functions for my compiler support keeping the assembly instructions the same). But the audio output was not clear at all. Then I had selected FPM_DEFAULT. With that I am able to hear a feeble (but with noise) audio. /**** mad_f_mul ****/ #define FPM_ARM # define SIZEOF_INT 4 # define SIZEOF_LONG 4 # define SIZEOF_LONG_LONG 8 # define MAD_F_FRACBITS 28 #define MAD_F_SCALEBITS MAD_F_FRACBITS static mad_fixed_t mad_f_mul(mad_fixed_t x,mad_fixed_t y) { mad_fixed_t result; mad_fixed64hi_t hi; mad_fixed64lo_t lo; _asm(-1000," smull %0,%1,%3,%4 movs %0,lsr(%0,%5) adc %2,%0,lsl(%1,%6) ", __reg_gen(__obj_modify(lo)), __reg_gen(__obj_modify(hi)), __reg_gen(__obj_assign(result)), __reg_gen(x), __reg_gen(y), MAD_F_SCALEBITS, (32 - MAD_F_SCALEBITS) ); return result; } /****Ends****/ I like to know if I am missing something? Thanks Balaji Shanmugam _________________________________________________________________ Reach out to millions of buyers. http://go.msnserver.com/IN/52047.asp With zero investment.

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determining the first scale factor band with short windows
by Rafael Ávila de Espíndola 13 Jul '04

13 Jul '04

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Rob, I noticed that libmad count up to 36 in III_reorder to determine the first scale factor band that should be reordered in a mixed block. The attached patch precomputes this. I don't expect it to improve performance in any measurable way but (IMHO) it makes the code a bit easier to read. Thanks for libmad, Rafael Ávila de Espíndola -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.4 (GNU/Linux) iD8DBQFA8zvTLlrfGJ8JUHwRAlmMAJwKzXgUoXPUM+U8u2l4cByyHPjRYgCfWuEZ Jw7Qs4lVqbC9wNHixrDaqFs= =Pu6p -----END PGP SIGNATURE-----

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16bit MAD
by Erik Gustavsson 02 Jul '04

02 Jul '04

Would it be possible to convert MAD into a (limited compliance) decoder using mostly 16bit fixed-point math? Specifically I'd like to port MAD to a ADI Blackfin DSP, which has 32bit registers and ALU but only 16x16 multipliers (with 40bit accumulators).

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RE: [mad-dev] A little help needed on code optimisation to deal with delay slots
by Joolz [RSD] 02 Jul '04

02 Jul '04

I would like to have a look please Gregory. I have already started the port // MLO( x, y); ld %r0, [x] ld %r1, [y] mul64 %r0, %r1 ld %r2, [%mhi] // MLA( x1, y1); ld %r0, [x1] ld %r1, [y1] mul64 %r0, %r1 add %r2, [%mhi] // MLA( x2, y2); ld %r0, [x2] ld %r1, [y2] mul64 %r0, %r1 add %r2, [%mhi] Into ld %r0, [x] ld %r1, [y] mul64 %r0, %r1 ld %r0, [x1] ld %r1, [y1] ld %r2, [%mhi] mul64 %r0, %r1 ld %r0, [x2] ld %r1, [y2] add %r2, [%mhi] mul64 %r0, %r1 Saves 2 cycles per multiply, only another 8 to go Best Regards Julian Gardner RSD Communications Ltd ============================ Please do not send me any html messages as these may be deleted at our mail server without notice to sender or recipient. Please ONLY send me file attachments with any messages with extensions .zip, .rar, or .pdf as any other file types may be deleted at our mail server without notice to sender or recipient. > -----Original Message----- > From: Grigory A. [mailto:Ryhor@tut.by] > Sent: Friday, July 02, 2004 2:34 AM > To: Joolz [RSD] > Cc: mad-dev(a)lists.mars.org > Subject: Re: [mad-dev] A little help needed on code > optimisation to deal with delay slots > > Hi Joolz! > > You have BIG problem :) 10 cycles stall every mul. > The most "multiplication consuming" functions are > - IMDCT - actually it isn't too much > - synthesis filter > > last one has a lot of multiplication > all other relatively free from mult operation. May be stereo > processing has a little. > > If you have short of calculation power I can recommend you to > do same as I did. I've separated calculation functions and > implement them on asm. > I can send the source code of of MAD with such improvements > that I used for > - tms320vc55xx and > - sp3R5 3DSP cores. > > > -- > Best regards, > Grigory mailto:Ryhor@tut.by > >

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A little help needed on code optimisation to deal with delay slots
by Joolz [RSD] 02 Jul '04

02 Jul '04

I have ported the library to our hardware platform ( a set-top box with ide interface and ARC8 processor) but I have found that we are running short of horsepower. The problem stems from the fact that when I use the multiplier it stalls the chip for 10cycles on every multiply mul64 %r0, %r1 lsl %r0, [%mhi], 4 --> Stalls until multiplier finishes I have started looking at reordering the code as I can use other instructions in these 10 cycles <from synth.c dct32:282> // t69 = t33 + t34; t89 = MUL(t33 - t34, costab4); mad_f_mul_j( t33 - t34, costab4); // We have 10 cycles to wait t69 = t33 + t34; // 2-3 t70 = t35 - t36; // 2-3 t89 = mad_f_mul_r(); // t70 = t35 + t36; t90 = MUL(t35 - t36, costab28); // t70 = t35 - t36; mad_f_mul_j( t70, costab28); // We have 10 cycles to wait t70 = t35 + t36; // 2-3 t113 = t69 + t70; // 2-3 t71 = t37 - t38; // 2-3 t90 = mad_f_mul_r(); This gives me savings of around 6 cycles per multiply, so we only lose 4 cycles. What I would like know is which routine/s should I convert first to save the maximum amount of time Joolz

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